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1/30 L6997S june 2004 1 features from 3v to 5.5v v cc range minimum output voltage as low as 0.6v 1v to 35v input voltage range constant on time topology very fast load transients 0.6v, 1% vref selectable sinking mode lossless current limit, available also in sinking mode remote sensing ovp,uvp latched protections 600 a typ quiescent current power good and ovp signals pulse skipping at ligth loads 94% efficiency from 3.3v to 2.5v 2 applications networking dc/dc modules distributed power mobile applications chip set, cpu, dsp and memories supply 3 description the device is a high efficient solution for networking dc/dc modules and mobile applications compatible with 3.3v bus and 5v bus. it's able to regulate an output voltage as low as 0.6v. the constant on time topology assures fast load tran- sient response. the embedded voltage feed-forward provides nearly constant switching frequency opera- tion in spite of a wide input voltage range. an integrator can be introduced in the control loop to reduce the static output voltage error. the remote sensing improves the static and dynamic regulation, recovering the wires voltage drop. pulse skipping technique reduces power consump- tion at light loads. drivers current capability allows output currents in excess of 20a. step down controller for low voltage operations figure 2. minimum component count application L6997S shdn 3.3v int vdr vsense ovp vref gnd gndsense vfb vcc ss osc 0.6v pgood pgnd lgate phase hgate ilim boot rilim css cvref hs ls rin1 rin2 cin cboot dboot l cout ro1 ro2 ds rev. 1 figure 1. package table 1. order codes part number package L6997S tssop20 L6997Str tape & reel tssop20
L6997S 2/30 table 2. absolute maximum ratings table 3. thermal data figure 3. pin connection (top view) symbol parameter value unit v cc v cc to gnd -0.3 to 6 v v dr v dr to gnd -0.3 to 6 v hgate and boot, to phase -0.3 to 6 v hgate and boot, to pgnd -0.3 to 42 v v phase phase -0.3-to 36 v lgate to pgnd -0.3 to v dr +0.3 v ilim, vfb, vsense, noskip, shdn, pgood, ovp, vref, int, gnd sense to gnd -0.3 to v cc +0.3 v boot, hgate and phase pins maximum withstanding voltage range test condition:cdf-aec-q100-002 ?human body model? accepatance criteria: ?normal performance? 750 v other pins 2000 v p tot power dissipation at t amb = 25c 1 w t stg storage temperature range -40 to 150 c symbol parameter value unit r th j-amb thermal resistance junction to ambient 125 c/w t j junction operating temperature range -40 to 125 c table 4. pin function n name description 1 noskip connect to v cc to force continuous conduction mode and sink mode. 2 gndsense remote ground sensing pin 3 int integrator output. short this pin to vfb pin and connect it via a capacitor to v out to insert the integrator in the control loop. if the integrator is not used, short this pin to vref. 4 vsense this pin must be connected to the remote output voltage to detect overvoltage and undervoltage conditions and to provide integrator feedback input. gndsense int ovp shdn ilim osc vcc noskip pgood lgate pgnd vdr phase hgate boot 1 3 2 4 5 6 7 8 9 18 17 16 15 14 13 19 20 10 ss gnd 11 12 vref vfb tssop20 int vsense
3/30 L6997S 5v cc ic supply voltage. 6 gnd signal ground 7 vref 0.6v voltage reference. connect a ceramic capacitor (max. 10nf) between this pin and ground. this pin is capable to source or sink up to 250ua 8 vfb pwm comparator feedback input. short this pin to int pin to enable the integrator function, or to vsense to disable the integrator function. 9 osc connect this pin to the input voltage through a voltage divider in order to provide the feed- forward function don?t leave floating. 10 ss soft start pin. a 5 a constant current charges an external capacitor. itsvalue sets the soft- start time don?t leave floating. 11 ilim an external resistor connected between this pin and gnd sets the current limit threshold don?t leave floating.. 12 shdn shutdown. when connected to gnd the device and the drivers are off. it cannot be left floating. 13 ovp open drain output. during the over voltage condition it is pulled up by an external resistor. 14 pgood open drain output. it is pulled down when the output voltage is not within the specified thresholds. otherwise is pulled up by external resistor. if not used it can be left floating. 15 pgnd low side driver ground. 16 lgate low side driver output. 17 v dr low side driver supply. 18 phase return path of the high side driver. 19 hgate high side driver output. 20 boot bootstrap capacitor pin. high side driver is supplied through this pin. table 5. electrical characteristics (v cc = v dr = 3.3v; t amb = 0c to 85c unless otherwise specified) symbol parameter test condition min. typ. max. unit supply section vin input voltage range vout=vref fsw=110khz iout=1a 1 35 v v cc , v dr 35.5v v cc turn-onvoltage 2.86 2.97 v turn-off voltage 2.75 2.9 v hysteresis 90 mv iqv dr drivers quiescent current vfb > vref 7 20 a iqvcc device quiescent current vfb > vref 400 600 a shutdown section shdn device on 1.2 v device off 0.6 v i sh v dr drivers shutdown current shdn to gnd 5 a i sh v cc devices shutdown current shdn to gnd 1 15 a soft start section i ss soft start current v ss = 0.4v 4 6 a ? v ss active soft start and voltage 300 400 500 mv table 4. pin function (continued) n name description
L6997S 4/30 current limit and zero current comparator i lim input bias current r ilim = 2k ? to 200k ? 4.655.4 a zero crossing comparator offset phase-gnd -2 2 mv k ilim current limit factor 1.6 1.8 2 a on time ton on time duration v ref =v sense osc=125mv 720 800 880 ns v ref =v sense osc=250mv 370 420 470 ns v ref =v sense osc=500mv 200 230 260 ns v ref =v sense osc=1000mv 90 115 140 ns off time t offmin minimum off time 600 ns k osc /t offmin osc=250mv 0.20 0.40 voltage reference vref voltage accuracy 0 a < i ref < 100 a 0.594 0.6 0.606 v pwm comparator input voltage offset -2 +2 mv i fb input bias current 20 na integrator over voltage clamp v sense = v cc 0.62 0.75 0.88 v under voltage clamp v sense = gnd 0.45 0.55 0.65 v integrator input offset voltage v sense -v ref -4 -4 mv i vsense input bias current 20 na gate drivers high side rise time v dr =3.3v; c=7nf hgate - phase from 1 to 3v 50 90 ns high side fall time 50 100 ns low side rise time v dr =3.3v; c=14nf lgate from 1 to 3v 50 90 ns low side fall time 50 90 ns p good uvp/ovp protections ovp over voltage threshold with respect to v ref 118 121 124 % uvp under voltage threshold 67 70 73 % upper threshold (v sense -v ref ) v sense rising 110 112 116 % lower threshold (v sense -v ref ) v sense falling 858891 % v pgood i sink =2ma 0.2 0.4 v table 5. electrical characteristics (continued) (v cc = v dr = 3.3v; t amb = 0c to 85c unless otherwise specified) symbol parameter test condition min. typ. max. unit
5/30 L6997S figure 4. functional & block diagram + + - phase sensegnd gm vsense vsense vsense vsense - - noskip 0.6v reference chain int v + - v - + delay toff min in in - phase vsense vref + - + - + + 1.416 1.236v bandgap + mode no-skip no-skip osc ls control vref vref pwm comparator fb - + vref comparator positive current limit vsense pgnd lgate vdr phase hgate boot gnd vcc ovp pgood shdn ss ilim osc comparator negative current limit ls and hs anti-cross-conduction comparators comp v(lgate)<0.5v comp v(phase)<0.2v hs control 0.05 ilim 0.05 overvoltage comparator undervoltage comparator - + - ic enable sr 1.12 vref control soft-start power management pgood comparators 0.925 vref 1.075 vref - + 0.6 vref 5 ua level shifter vcc zero-cross comparator one-shot one-shot ton min to n ton= kosc v(vsense)/v(osc) vsense mode phase hs driver ls driver to n vcc v one-shot osc ton= kosc v(vsense)/v(osc) out s r q r s q r s q
L6997S 6/30 4 device description 4.1 constant on time pwm topology figure 5. loop block schematic diagram the device implements a constant on time control sc heme, where the ton is the high side mosfet on time duration forced by the one-shot generator. the on time is directly proportional to vsense pin voltage and in- verse to osc pin voltage as in eq1: (1) where k osc = 180ns and is the internal propagation delay time (typ. 40ns). the system imposes in steady state a minimum on time corresponding to v osc = 1v. in fact if the v osc voltage increases above 1v the cor- responding ton will not decrease. connecting t he osc pin to a voltage partition from v in to gnd, it allows a steady-state switching frequency f sw independent of v in . it results: (2) where (3) (4) the above equations allow setting the frequency divider ratio osc once output voltage has been set; note that such equations hold only if v osc <1v. further the eq2 shows how the system has a switching frequen- cy ideally independent from the input voltage. the delay introduces a light dependence from v in . a mini- mum off-time constraint of about 500ns is introduced in order to assure the boot capacitor charge and to q vsense r3 r4 r2 r1 r s vout vin hgate lgate q osc fb vref hs ls ds pwm comparator ffsr one-shot generator - + t on k osc v sense v osc --------------------- - + = f sw v out v in -------------- - 1 t on ----------- osc out -------------- - 1 k osc --------------- osc f sw k osc out == = osc v osc v in --------------- r 2 r 2 r 1 + -------------------- == out v fb v out -------------- - r 4 r 3 r 4 + -------------------- ==
7/30 L6997S limit the switching frequency after a load transient as well as to mask pwm comparator output against noise and spikes. the system has not an internal clock, because this is a hyst eretic controller, so the turn on pulse will start if three conditions are met contemporarily: the fb pin voltage is lower than the reference voltage, the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit value). the voltage at the osc pin must range be tween 50mv and 1v to ensure the system linearity. 4.2 closing the loop the loop is closed connecting the output voltage (or the output divider middle point) to the fb pin. the fb pin is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage (0.6v typ.) as in figure 5. when the fb goes lower than the reference voltage, the pwm comparator output goes high and sets the flip-flop output, turning on the high side mosfet. this condition is latched to avoid noise. after the on-time (calculated as described in the previous section) the system resets the flip-flop, turns off the high side mosfet and turns on the low side mosfet. for more details refers to the figure 4. the voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of dc error. further the system regulates the output volt age valley value not the average, as shown in figure 6. so, the voltage ripple on the output capacitor is a source of dc static error (well as the pcb traces). to com- pensate the dc errors, an integrator network must be introduced in the control loop, by connecting the output voltage to the int pin through a capacitor and the fb pin to the int pin directly as in figure 7. the internal in- tegrator amplifier with the external capacitor c int1 introduces a dc pole in the control loop. c int1 also provides an ac path for output ripple. figure 6. valley regulation the integrator amplifier generates a current, proportional to the dc errors, that increases the output capacitance voltage in order to compensate the total static error. a voltage clamp within the device forces anint pin voltage range (v ref -50mv, v ref +150mv). this is useful to avoid or smooth output voltage overshoot during a load transient. also, this means that the integrator is capable of recovering output error due to ripple when its peak- to-peak amplitude is less than 150mv in steady state. in case the ripple amplitude is larger than 150mv, a capacitor c int2 can be connected between int pin and ground to reduce ripple amplitude at int pin, otherwise the integrator will operate out of its linear range. choose c int1 according to the following equation: (5) where g int =50 s is the integrator transconductance, out is the output divider ratio given from eq4 and f u is the close loop bandwidth. this equation holds if c int2 is connected between int pin and ground. c int2 is given by: time vout vref dc error offset c int1 g int out ? 2 f u ?? ------------------------------- =
L6997S 8/30 (6) where ? v out is the output ripple and ? v int is the required ripple at the int pin (100mv typ). figure 7. integrator loop block diagram respect to a traditional pwm controller, that has an intern al oscillator setting the switching frequency, in a hys- teretic system the frequency can change with some parameter s. for example, while in a standard fixed switch- ing frequency topology, the increase of the losses (increasing the output current, for example) generates a variation in the on time and off time, in a fixed on time topology , the increase of the losses generates only a variation on the off time, changing the switching frequency. in the device is implemented the voltage feed- forward circuit that allows constant switching frequency during steady-sate operation and withinthe input range variation. any way there are many factors affecting switching frequency accuracy in steady-state operation. some of these are internal as dead times, which depends on high side mosfet driver. others related to the external components as high side mosf et gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side rdson and inductor parasitic resistance. during a positive load transient, (the output current increases), the converter switches at its maximum frequency (the period is ton+toffmin) to recover the output vo ltage drop. during a negative load transient, (the output current decreases), the device stops to switch (high side mosfet remains off). 4.3 transition from pwm to pfm/psk to achieve high efficiency at light load conditions, pf m mode is provided. the pfm mode differs from the pwm mode essentially for the off phase; the on phase is the same. in pfm after a on cycle the system turns-on the low side mosfet until the inductor current goes down ze ro, when the zero-crossing comparator turns off the low side mosfet. in pwm mode, after on cycle, the system keeps the low si de mosfet on until the next turn- on cycle, so the energy stored in the output capacitor will flow through the low side mosfet to ground. the pfm mode is naturally implemented in an hysteretic contro ller enabling the zero current comparator by en- abling, in fact in pfm mode the system reads the output voltage with a comparator and then turns on the high side mosfet when the output voltage goes down to reference value. the device works in discontinuous mode c int2 c int1 --------------- - v out ? ? v int ------------------ = pcb traces load from vsense q cint1 r1 int vref fb ds r s vout vin hgate lgate q osc vref one-shot generator ffsr pwm comparator vsense gndsense r2 cint2 hs ls integrator amplifier + - - + + -
9/30 L6997S at light load and in continuous mode at high load. the tran sition from pfm to pwm occurs when load current is around half the inductor current ripple. this threshold value depends on v in , l, and v out . note that the higher the inductor value is, the smaller the threshold is. on t he other hand, the bigger the inductor value is, the slower the transient response is. the pfm waveforms may appear more noisy and asynchronous than normal opera- tion, but this is normal behaviour mainly due to the very low load. if the pfm is not compatible with the applica- tion it can be disabled connecting to v cc the noskip pin. 4.4 softstart after the device is turned on the ss pin voltage begins to increase and the system starts to switch. the softstart is realized by gradually increasing the current limit thres hold to avoid output overvoltage. the active soft start range for the v ss voltage (where the output current limit increase linearly) is from 0.6v to 1v. in this range an internal current source (5 a typ) charges the capacitor on the ss pin; the reference current (for the current limit comparator) forced through ilim pin is proportional to ss pin voltage and it saturates at 5 a (typ.). when ss voltage is close to 1v the maximum current limit is acti ve. output protections ovp & uvp are disabled until the ss pin voltage reaches 1v (see figure 8). once the ss pin voltage reaches the 1v value, the voltage on ss pin doesn't impact the system operation any- more. if the shdn pin is turned on before the supplies, the power section must be turned on before the logic section. while if the supplies are applied with the shnd pin off, the start up sequence doesn't meter. figure 8. soft -start diagram because the system implements the soft start by controlling the inductor current, the soft start capacitor should be selected based on of the output capacitance, the current limit and the soft start active range ( ? v ss ). in order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before the soft start voltage reaches the under voltage value (1v). after this uvp and ovp are enable. the time necessary to charge the ss capacitor up to 1v is given by: (7) in order to calculate the output voltage chargin time it should be considered that the inductor current function can be supposed linear function of the time. (8) time time 0.6v maximum current limit soft-start active range 5 a 4.1v 1v ilim current vss t ss c ss () 1v iss -------- c ss ? = i l t,c ss () r ilim /r dson k ilim i ss t ??? () v ss c ss ? ? () -------------------------------------------------------------------------- - =
L6997S 10/30 so considering zero the output load the output voltage is given by: (9)) indicating with v out the final value, the output charging time can be estimated as: (10) the minimum c ss value is given imposing this condition: t out =t ss (11) 4.5 current limit the current limit comparator senses the i nductor current through t he low side mosfet rds on drop and com- pares this value with the ilim pin voltage value. while t he current is above the current limit value, the control inhibits the high side mosfet turn on. to properly set the current limit threshold, it should be not ed that this is a valley current limit. the average cur- rent depends on the inductor value, v in v out and switching frequency. the average output current in current limit is given by: (12) thus, to set the current threshold, choose rilim according to the following equation: (13) in overcurrent conditions the system keeps the current constant until the output voltage meets the undervoltage threshold. the negative valley current limit, for the sink m ode, is set automatically at the same value of the pos- itive valley current limit. the average negative current limit differs from the positive average current limit by the ripple current; this difference is due to the valley control technique. the current limit system accuracy is function of the precision of the resistance connected to the ilim pin and the low side mosfet rds on accuracy. moreover the voltage on ilim pin must range between 10mv and 1v to ensure the system linearity. figure 9. current limit schematic v out t,c ss () qt,c ss () c out ------------------------ - r ilim /r dson k ilim i ss t 2 ??? () c out v ss c ss 2 ?? ? ? () ----------------------------------------------------------------------------- == v out c ss () v out c out v ss c ss 2 ?? ? ?? () r ilim /r dson k ilim i ss ?? () --------------------------------------------------------------------------- - 0.5 = i out cl i max valley i ? 2 ---- - + = i max valley r ilim rds on ----------------- k ilim ? = positive and negative current limit r ilim 5 a current comparator to logic pgn d phase to inductor ls
11/30 L6997S 4.6 protection and fault the load protection is realized by using the vsense pin. both ovp and uvp are latched, and the fault condition is indicated by the pgood and the ovp pins. if the output voltage is between the 89% (typ.) and 110% (typ) of the regulated value, pgood is high. if a hard overvoltage or an undervoltage occurs, the device is latched: low side mosfet and, high side mo sfet are turned off and pgood goes low. in case the system detects an overvoltage the ovp pin goes high. to recover the functionality the device must be shut down and restarted the shdn pin, or by removing the sup- ply, and restarting the devicewith the correct sequence. 4.7 drivers the integrated high-current drivers allow using different size of power mosfet, mainta ining fast switching tran- sitions. the driver for the high side mosfet uses the boot pin for supply and phase pin for return (floating driver). the driver for the low side mosfet uses the vdr pin for the supply and pgnd pin for the return. the drivers have the adaptive anti-cross-conduction protection, which prevents from having bothhigh side and low side mosfet on at the same time, avoiding a high cu rrent to flow from vin to gnd. when high side mosfet is turned off the voltage on the phase pin begins to fall; the low side mosfet is turned on only when the volt- age on phase pin reaches 250mv. when low side is turned off, high side remains off until lgate pin voltage reaches 500mv. this is important since the driver can work properly with a large range of external power mos- fets. the current necessary to switch the external mosfets flows through the device, and it is proportional to the mosfet gate charge the switching frequency and the driver voltage. so the power dissipation of the device is function of the external power mosf et gate charge and switching frequency. (14) the maximum gate charge values for the low side and high side are given by: (15) (16) where f sw0 = 500khz. the equations above are valid for t j = 150c. if the system temperature is lower the q g can be higher. for the low side driver the max output gate charge meets another limit due to the internal traces degradation; in this case the maximum value is q maxls = 125nc. the low side driver has been designed to have a low resistance pull-down transistor, approximately 0.5 ohms. this prevents undesired ls mosfet turn on during the fa st rise-time of the pin phase, due to the miller ef- fect. when the 3.3v bus is used to supply the drivers, ult ra logic level mo sfets should be selected , to be sure that the mosfets work in properly way. p driver v cc q gtot f sw ?? = q maxhs f sw0 f sw ------------ - 75nc ? = q maxls f sw0 f sw ------------ - 125nc ? =
L6997S 12/30 5 application information 5.1 5a demo board description the demo board shows the device operation in this condition: vi n from 3.3v to 5v, i out =5a v out =1.25v. the evaluation board let use the system with 2 different voltages (v cc the supply for the ic and v in the power input for the conversion) so replacing the input capacitors t he power input voltage could be also 35v. when instead the input voltage (v in ) is equal to the v cc it should be better joining them with a 10 ? resistor in order to filter the device input voltage. on the topside demo there are two different jumpers: one jumper, near the ovp and pow- er good test points, is used to shut down the device; when the jumper is present the device is in shutdown mode, to run the device remove the jumper. the other jumper, near the v ref test point, is used to set the pfm/ psk mode. when the jumper is present, at light load, the sy stem will go in pfm mode; if there is not the jumper, at light load, the system will remain in pwm mode. in the demo bottom side there are two others different jump- ers. they are used to set or remove the integrator configuration. when the jumpers named with int label are closed and the jumpers named with the noint label are open the integrator configuration is set. some- times the integrator configuration needs a low frequency filt er the to reduce the noise interaction. in this case instead close the int jumpers put there a resistor and after a capacitor to ground (as in the schematic diagram); the pole value is around 500khz but it should be higher enough than the switching frequency (ten times). on the opposite when the jumpers named with the noint are closed and the jumpers named with int are open the non integrator configuration is selected. refer to the table 1 and 2 for the jumpers connection. figure 10. demoboard schematic diagram c14,c15 r3 r10 tp1 tp2 c10 r6 q1 d2 tp3 c2 c6 r8 c12 c9 r9 r1 d1 r2 r5 sd ns l1 r7 c7,c13 c11 c4 r4 rn c3 c1 q2 cn int int noint noint c5 c8 vcc shdn vref osc noskip vdr int vfb gndsense ss boot ilim hgate phase lgate pgnd gnd vsense ovp pgood vcc vout gndout gndin viin L6997S j1
13/30 L6997S 5.2 jumper connection table 6. jumper connection with integrator * this component is not necessary, depends from the output esr capacitor. see the integrator section. table 7. jumper connection without integrator 5.3 demoboard layout real dimensions: 4,7 cm x 2,7 cm (1.85 inch x 1. 063 inch) component connection c1 mounted c2 mounted * int close noint open component connection c1 not mounted c2 not mounted int open noint close figure 11. top side components placement figure 12. bottom side jumpers distribution figure 13. top side layout figure 14. bottom side layout
L6997S 14/30 table 8. pcb layout guidelines goal suggestion to minimize radiation and magnetic coupling with the adjacent circuitry. 1) minimize switching current loop areas. (for example placing c in , high side and low side mosfets, shottky diode as close as possible). 2) place controller placed as close as possible to the power mosfets. 3) group the gate drive components (boot cap and diode) near the ic. to maximize the efficiency. keep power traces and load connections short and wide. to ensure high accuracy in the current sense system. make kelvin connection for phase pin and pgnd pin and keep them as close as possible to the low side mosfets. to reduce the noise effect on the ic. 1) put the feedback component (like output divider, integrator network, etc) as close as possible to the ic. 2) keep the feedback traces parallel and as close as possible. moreover they must be routed as far as possible from the switching current loops. 3) make the controller ground connection like the figure 8. table 9. component list the component list is shared in two sections: the first for the general-purpose component, the second for power section: part name value dimension notes general-purpose section resistor r1, r5, r9, r10 33k ? 0603 pull-up resistor r2 1k ? 0603 output resistor divider (to set output voltage) r3 1.1k ? 0603 r4 0603 input resistor divider (to set switching frequency) r6 470k ? 0603 r7 0 ? 0603 r8 0603 current limit resistor capacitor c1 330pf 0603 first integrator capacitor c2 n.m. 0603 second integrator capacitor c3 1nf 0603 c4 100nf 0603 c5 1 ftantalum c6 10nf 0603 c9 10nf 0603 softstart capacitor c10 100nf 0603 c11 100nf 0603 c8, c12 47pf 0603 diode d1 bar18 power section input capacitors c7, c13 47 f ecj4xf0j476z pa n a s o n i c
15/30 L6997S notes: 1. n.m.=not mounted 2. the demoboard with this component list is set to give: v out = 1.25v, f sw = 270khz with an input voltage around v in = v cc = 3.3v-5v and with the integrator feature. 3. the diode efficiency impact is very low; it is not a necessary component. 4. all capacitors are intended ceramic type otherwise specified. 5.4 efficiency curves source mode v in = 3.3v v out = 1.25v f sw = 270khz figure 15. efficiency vs output current part name value dimension notes output capacitors c14, c15 220 f 2r5tpe220m poscap inductor l1 2.7 h do3316p-272hc coilcraft power mos q1,q2 sts5dnf20v stmicroelectronics double mosfet in sigle package diode d2 stps340u stmicroelectronics 3 table 9. component list (continued) the component list is shared in two sections: the first for the general-purpose component, the second for power section: 0,0 10,0 20,0 30,0 40,0 50,0 60,0 70,0 80,0 90,0 100,0 0,0 1,0 2,0 3,0 4,0 5,0 6,0 current [a] eff [%] pfm mode pw m mo d e
L6997S 16/30 6 step by step design application conditions: v in = 3.3v, 10% v out = 1.25v i out = 5a f sw = 270khz 6.1 input capacitor. a pulsed current (with zero average value) flows through the input capacitor of a buck converter. the ac com- ponent of this current is quite high and dissipates a considerable amount of power on the esr of the capacitor: (17) the rms current, which the capacitor must provide, is given by: (18) where is the duty cycle of the application neglecting the last term, the equation reduces to: (19) which maximum value corresponds to to = 1/2 and is equal i out /2 therefore, in worst case, the input capacitors should be selected with a rms ripple current rating as high as half the respective maximum output current. electrolytic capacitors are the most used because t heyare the cheapest ones and are available with a wide range of rms current ratings. the only drawback is that, for a givenripple current rating, they are physically larg- er than other capacitors. very good tantalum capacitors ar e coming available, with very low esr and small size. the only problem is that they occasionally can burn if subjected to very high current during the charge. so, it is better avoid this type of capacitors for the input filter of the device. in fact, they can be subjected to high surge current when connected to the power supply. if available for the requested capacitance value and voltage rating, the ceramic capacitors have usually a higher rms current rating for a given physical dimension (due to the very low esr). the drawback is the quite high cost. possible solutions: with our parameter from the equation 3 it is found: icin rms = 2.42a 6.2 inductor to define the inductor, it is necessary to determine firs tly the inductance value. its minimum value is given by: (20) where rf = ? i/i out (basically it is approximately 30%). 10 f c34y5u1e106zte12 tokin 22 f jmk325bj226mm taiyo-yuden 47 f ecj4xf0j476z pa n a s o n i c 33 f c3225x5r0j476m tdk p cin esr cin iout 2 vin vin vout ? () ? vin 2 ----------------------------------------------- - ?? = icin rms iout 2 1 ? () 12 ------ i l ? () 2 + = icin rms iout 1 ? () = lmin v o vin max v o ? () ? f sw i out rf vin max ? ?? -------------------------------------------------------------- -
17/30 L6997S with our parameters: lmin 2 h the saturation current must be higher then 5a 6.3 output capacitor and ripple voltage the output capacitor is selected based on both static a nd dynamic output voltage accuracy. the static output voltage accuracy depends mostly on the ers of the output capacitor, while the dynamic accuracy usually de- pends both on the esr and capacitance value. if the static precision is 1% for the 1.25v output voltage, the output ripple is 12.5mv. to determine the esr value from the output precision is necessary to calculate the ripple current: (21) where f sw = 270khz. from the eq. above the ripple current is around 1.25a. so the esr is given by: (22) the dynamic specifications are sometimes more relaxed than the static requirements, anyway a minimum out- put capacitance must be ensured to avoid output voltage variation due to the charge and discharge of cout dur- ing load transients. to allow the device control loop to work properly, the zero introduced by the output capacitor esr ( = esr cout) must be at least ten times smaller than switch ing frequency. low esr tantalum capacitors, which esr zero is close to ten khz, are suitable for output filtering. output capacitor value c out and its esr, esrc out , should be large enough and small enough, respectively, to keep output voltage within the accuracy range during a load transient, and to give the device a minimum signal to noise ratio. the current ripple flows through the output capacitors, so the should be calculated also to sustain this ripple: the rms current value is given by eq. 18. (23) but this is usually a negligible constrain. possible solutions: multilayer capacitors can not be used because their very low esr. 6.4 mosfet?s and schottky diodes a 3.3v bus powers the gate drivers of the device, the us e ultra low level mosfet is highly recommended, es- pecially for high current applicati ons. the mosfet breakdown voltage v brdss must be greater than vinmax with a certain margin. the rds on can be selected once the allowable power dissipation has been established. by selecting identical 330 f eefue0d331r pa n a s o n i c 220 f2r5tpe220m poscap i ? vin vo ? l ---------------------- - vo vin --------- t sw ?? = esr v ripple ? i ? 2 ---- - --------------------- 25mv 1.25 ---------------- = 20m ? == icout rms 1 23 ---------- - i l ? =
L6997S 18/30 power mosfet for us and ls, the total power they dissip ate does not depend on the duty cycle. thus, if pon is this power loss (few percent of the rated output power), the required rds on (@ 25 c) can be derived from: (24) is the temperature coefficient of rds on (typically, = 510 -3 c -1 for these low-voltage classes) and t the admitted temperature rise. it is worth noticing, however, that generally the lower rds on , the higher is the gate charge q g , which leads to a higher gate drive consumption. in fact, each switching cycle, a charge q g moves from the input source to ground, resulting in an equivalent drive current: (25) a schottky diode can be added to increase the system e fficiency at high switching frequency (where the dead times could be an important part of total switching period). this optional diode must be placed in parallel to the synchronous rectifier must have a reverse voltage vrrm greater than vin max . the current size of the diode must be selected in order to keep it in safe operating condi- tions. in order to use less space than possible, a double mosfet in a single package is chosen: sts5dnf20v 6.5 output voltage setting the first step is choosing the output divider to set the output voltage. to select this value there isn't a criteria, but a low divider network value (around 100 ? ) decries the efficiency at low current; instead a high value divider network (100k ? ) increase the noise effects. a network divider values from 1k ? to 10k ? is right. we chose: r3 = 1k ? r2 = 1.1k ? the device output voltage is adjustable by connecting a voltage divider from output to vsense pin. minimum output voltage is v out =vref=0.6v. once output divider and frequency divider have been designed as to obtain the required output voltage and switching frequency, the following equation gives the smallest input voltage, which allows L6997S to regulate (which corresponds to t off =t offmin ): (26) 6.6 voltage feedforward from the equations 1,2 and 3, choosing the switching fr equency of 270khz the resistor divider can be selected. for example: r3 = 470k ? r4 = 8.5k ? 6.7 current limit resistor from the equation 8 the valley current limit can be set considering the rds on sts5dnf20v and i cir = 5a: r8 = 120k ? 6.8 integrator capacitor let?s assume f u = 15khz, v out = 1.25v. since v ref = 0.6v, from equation 2, of the device description, it follows o ut = 0.348 and, from equation 5 it follows c = 250pf. the output ripple is around 22mv, so th e system doesn't need the second integrator capac- itor. rds on p on iout 2 1 t ? ? + () ? ------------------------------------------------ - = iq qg f sw ? = 1 osc out -------------- - 1 k osc t off,min ------------------------- - ?? ?? ?? max --------------------------------------------- - ? ? <
19/30 L6997S 6.9 soft start capacitor considering the soft start equations (eq. 11) at page 10, it can be found: c ss = 150pf the equations are valid without load. when an active load is present the equations result more complex; further some active loads have unexpected effect, as higher cu rrent than the expected one during the soft start, can change the start up time. in this case the capacitor value can be selected on the application; anyway the eq11 gives an idea about the c ss value. 6.10 sink mode figure 16. efficiency vs output current 7 15a demo board description the evaluation board shows the device operation in these conditions: v in = 3.3v v out = 1.8v i out = 15a, f sw = 200khz without the integrator feature. the ev aluation board has two different input voltages: v cc [from 3v to 5.5v] used to supply the device and the v in [up to 35v] for the power conversion. in this way, changing the pow- er components configuration (c in , c out , mosfets, l) it is possible evaluate the device performance in differ- ent conditions. it is also possible to mount a linear regulator on board used to generate the v cc . on the top side are also present two switches and four jumpers. the tw o switches have different goals: the one nearest to the v cc is used to turn on/off the device when the v cc and v in are both present; the other one, near to r11 is used to turn on/off the pfm feature. the device can be tur ned on also with the power supply, but a correct start up sequence is mandatory. v in has to be raised first and then the v cc can be applied too. if the correct sequence is not respected the device will not start up. the jumpers are used to set the integrator feature and to use the remote sensing; for more information refers to the ju mpers table. sometimes when using the integrator config- uration a low frequency filter is required in order to reduce the noise interaction. the pole value should be at least five times higher than the switching frequency. the low pass filter should be inserted in this way: the re- sistor, in the place of the int jumper position and the c apacitor between the resistor and ground (refers to the schematic). 0,0 10,0 20,0 30,0 40,0 50,0 60,0 70,0 80,0 90,0 100,0 0,01,02,03,04,05,0 curr ent [a] eff [%]
L6997S 20/30 figure 17. L6997S schematic diagram 7.1 umpers connection table 10. jumper connection with integrator *this component is not necessary, depends from the output esr capacitor. see the integrator section. table 11. jumper connection without integrator component connection c4 mounted c7 mounted* int close noint open component connection c4 not mounted c7 not mounted int open noint close pgnd phase gndsense vsense lgate boot hgate vdr fb osc vcc vref noskip ovp pgood shdn v cc l6997 gnd ss int r10 r9 c13, c14, c15, c16, c17, c18 r3 r4 c5 r5 c22 c3 d1 c19 q1, q2, q3 q4, q5, q6 d2 c7 c8 c9 c10, c11 c12 c20 c21 r8 c23 noint int noint int c6 c25 c4 c7 c n r n tp1 tp2 tp3 r12 r11 r7 r6 v ou t c2 sw1 r13 c24 l v in L6997S
21/30 L6997S 7.2 demo board layout real dimensions: 5.7cm x 7.7cm (2.28inch x 3. 08inch) figure 18. pcb layout: bottom side figure 19. pcb layout: top side figure 20. internal ground plane figure 21. power & signal plane table 12. pcb layout guidelines goal suggestion to minimize radiation and magnetic coupling with the adjacent circuitry. 1) minimize switching current loop areas. (for example placing c in , high side and low side mosfets, shottky diode as close as possible). 2) place controller placed as close as possible to the power mosfets. 3) group the gate drive components (boot cap and diode) near the ic. to maximize the efficiency. keep power traces and load connections short and wide. to ensure high accuracy in the current sense system. make kelvin connection for phase pin and pgnd pin and keep them as close as possible to the low side mosfets. to reduce the noise effect on the ic. 1) put the feedback component (like output divider, integrator network, etc) as close as possible to the ic. 2) keep the feedback traces parallel and as close as possible. moreover they must be routed as far as possible from the switching current loops. 3) make the controller ground connection like the figure 8.
L6997S 22/30 table 13. component list the component list is shared in two sections: the first for the general-purpose component, the second for power section: part name value dimension notes general-purpose section resistor r1 n.m. 0603 output resistor divider for the linear regulator. r2 n.m. 0603 r3 560k ? 0603 input resistor divider (to set switching frequency) r4 5.6k ? 0603 r5 47 ? 0603 r6, r7, r11, r12 33k ? 0603 r8 62k ? 0603 current limit resistor (to set current limit) r9 2.7k ? 0603 output resistor divider (to set output voltage) r10 1.3k ? 0603 r13 220 ? 0603 capacitor c1 220nf 0805 c2 47 f kemet-16v c3 220nf 0805 c4 150pf 0603 first integrator capacitor c5 47pf 0603 c6 10nf 0603 c7 n.m. 0603 second integrator capacitor c19 220nf 0805 c20 220nf 0603 softstart capacitor c21 47pf 0603 c22 220nf 0805 c23 0603 n.m. c24 1nf 0603 c25 1 ftantalum diodes d1 bat54 25v power section output capacitors c11-c12 2x680 f t510x687(1)004as kemet output capacitor c8, c9, c10 n.m. input capacitors c13, c14, c16, c17, c15 c18 100 f ecj5yf0j1072 panasonic input capacitor 47 f ecj5yf1a4767 panasonic inductor l1 1.8 h etqf6f1r8bfa panasonic power mos q1,q2 si4442dy vishay siliconix q3 n.m. q5,q6 si4442dy vishay siliconix q4 n.m. integrated circuit u1 L6997S
23/30 L6997S 7.3 efficiency curves figure 22. efficiency vs output current table 14. efficiency curves for different applications (v in up to 25v) part name value dimension notes general-purpose section resistor r1 100 ? 0603 output resistor divider for the linear regulator. r2 300 ? 0603 r3 560k ? 0603 input resistor divider (to set switching frequency) r4 10k ? 0603 r5 47 ? 0603 r6, r7, r11, r12 33k ? 0603 r8 47k ? 0603 current limit resistor (to set current limit) r9 2,7k ? 0603 output resistor divider (to set output voltage) r10 1k ? 0603 r13 220 ? 0603 capacitor c1 220 nf 0805 c2 47 fkemet-16v c3 220nf 0805 c4 150pf 0603 first integrator capacitor c5 47pf 0603 c6 10nf 0603 c7 330pf 0603 second integrator capacitor c19 220nf 0805 c20 10nf 0603 softstart capacitor c21 47pf 0603 c22 220nf 0805 c23 0603 n.m. 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 output current (a) efficiency (%) vcc=vin=3.3v fsw=200khz vout=0.9v vout=1.2v vout=1.5v vout=1.8v vout=2.5v
L6997S 24/30 note: for the 25v to 12v conversion the inductor used is: 77120a core 7t. 7.4 efficiency curves part name value dimension notes c24 1nf 0603 c25 1 ftantalum diodes d1 bat54 25v power section output capacitors c11-c12 2x100 f b45197-a3107- k409 epcos output capacitor c8, c9, c10 n.m. input capacitors c13, c14, c16, c17, c15 c18 10 f c34y5u1e106z tokin input capacitor 10 f c3225y5v1e106z tdk 10 f ecj4xf1e106z pa n a s o n i c 10 f tmk325f106zh taiyo yuden inductor l1 3 h t50-52 core, 7t awg15 power mos q1,q2 sts11nf3ll stmicroelectronics q3 n.m. q5,q6 sts11nh3ll stmicroelectronics q4 n.m. diodes d2 stps2l25u stmicroelectronics 25v integrated circuit u1 L6997S table 14. efficiency curves for different applications (v in up to 25v) (continued) figure 23. efficiency vs output current figure 24. efficiency vs output current 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0.9v 1.2v 1.5v 1.8v 2.5v vo = 3.3v vin = vcc = 5v fsw = 200khz output current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 100 012345678910111213141516171819 output current (a) efficiency (%) vin = 12v vcc = 5v fsw = 200khz 0.9v 1.2v 1.5v 2.5v 3.3v vo = 5v 1.8v
25/30 L6997S figure 25. efficiency vs output current figure 26. efficiency vs output current 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 output current [a] eff [%] v out = 12v v in = 25v v cc = 5v f sw = 200khz v out = 5v v out = 3.3v 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 output current [a] eff [%] v out = 12v v in = 33v 7.5 ddr memory and termination supply double data rate (ddr) memories require a particular power management architecture. this is due to fact that the trace between the driving chipset and the memory input must be terminated with resistors. since the chipset driving the memory has a push pull output buffer, the termination voltage must be capable of sourcing and sink- ing current. moreover, the termination voltage must be equal to one half of the memory supply (the input of the memory is a differential stage requiring a reference bias midpoint) and in tracking with it. for ddri the memory supply is 2.5v and the termination voltage is 1.25vwhile for the ddrii the memory supply is 1.8v and the ter- mination voltage is 0.9v. figure 27 shows a complete ddrii memory and termination supply realized by using 2 x L6997S. the 1.8v section is powering the memory, while the 0.9v section is providing the termination voltage. figure 27. application idea: ddrii memory supply l6997 pgnd phase gndsense vsense lgate boot hgate vccdr fb osc vcc vref noskip ovp pgood shdn vcc l6997 gnd ss ilim u2 gndsense vsense fb pgnd lgate phase hgate boot vccdr vcc osc noskip int vref shdn pgood ovp gnd u1 ss ilim vin vcc int + - chipset memory supply vref bus termination network vddq 1.8v@15a vtt 0.9v@- 5a + r 2r 2r r sts8dnf3ll sts11nf3ll sts11nf3ll L6997S L6997S
L6997S 26/30 the current required by the memory and termina- tion supply, depends on the memory type and size. the figures 28 and 29 show the efficiency for the termination section of the application shown in fig. 27. figure 28. eff. vs. output current source mode figure 29. eff. vs output current sink mode 8 typical operating characteristics figure 30. load transient response from 0a to 5a. . figure 31. normal functionality in sink mode.. 70 75 80 85 90 95 100 0234567 output current (a) efficiency (%) 1 vout = 0.9v vcc = 5v fsw = 200khz vin = 12v vin=1.8v 60 65 70 75 80 85 90 95 100 01234567 output current (a) efficiency (%) vin=12v vin = 1.8v vin = 12v vout=0.9v vcc=5v fsw=200khz ch1-> inductor current ch2-> phase node ch3-> output voltage ch1-> inductor current ch2-> phase node ch3-> output voltage
27/30 L6997S figure 32. normal functionality in pwm mode. figure 33. normal functionality in pfm mode. figure 34. start up waveform with 0a load. figure 35. start up waveform with 5a load.. ch1-> inductor current ch2-> phase node ch3-> output voltage ch1-> inductor current ch2-> phase node ch3-> output voltage ch1-> inductor current ch2-> soft start voltage ch3-> output voltage ch1-> inductor current ch2-> soft start voltage ch3-> output voltage
L6997S 28/30 figure 36. tssop20 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.20 0.047 a1 0.050 0.150 0.002 0.006 a2 0.800 1.000 1.050 0.031 0.039 0.041 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 d (1) 6.400 6.500 6.600 0.252 0.256 0.260 e 6.200 6.400 6.600 0.244 0.252 0.260 e1 (1) 4.300 4.400 4.500 0.170 0.173 0.177 e 0.650 0.026 l 0.450 0.600 0.750 0.018 0.024 0.030 l1 1.000 0.039 k 0? (min.) 8? (max.) aaa 0.100 0.004 note: 1. d and e1 does not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. tssop20 0087225 (jedec mo-153-ac) thin shrink small outline package
29/30 L6997S table 15. revision history date revision description of changes june 2004 1 first issue.
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